Lattice Semiconductor ISPLSI 1016-60LT44: Architecture, Features, and Target Applications
The Lattice Semiconductor ISPLSI 1016-60LT44 represents a significant member of the high-density programmable logic family, designed for a wide array of digital system applications. As an in-system programmable (ISP) device, it offers designers flexibility and integration capabilities, making it a cornerstone for many complex designs in its era.
Architecture
At its core, the ISPLSI 1016 is built upon a Generic Logic Block (GLB) architecture. The device features 16 GLBs, each containing programmable AND/OR arrays and configurable registers. These blocks are interconnected through a Global Routing Pool (GRP), a central switch matrix that provides a highly flexible and efficient connectivity path between all GLBs and input/output pins. The chip also integrates 32 I/O cells, which are connected to the I/O Routing Pool (ORP), allowing for individual pin configuration as input, output, or bidirectional. This robust internal structure is managed by a dedicated programming control circuit, enabling in-system programmability via the IEEE 1149.1 (JTAG) interface.
Key Features
The ISPLSI 1016-60LT44 boasts a set of features that made it highly competitive. Its designation includes "60," indicating a 5.0ns pin-to-pin logic delay, allowing for high-speed operation. The "LT44" suffix denotes a 44-pin Thin Plastic Leaded Chip Carrier (TQFP) package, ideal for space-constrained applications. Key specifications include:
2,000 PLD Gates for moderate logic integration.
In-System Programmability (ISP) via a standard 4-wire JTAG port, facilitating rapid design iterations and field upgrades.
5V Operation, which was the industry standard at the time of its introduction.
Non-volatile E²CMOS® technology, ensuring the program is retained upon power-down without requiring an external configuration memory chip.
Full 100% tested and routable architecture, guaranteeing design implementation.
Target Applications
The combination of density, speed, and programmability made the ISPLSI 1016-60LT44 a versatile solution for numerous applications. It was primarily targeted at fulfilling glue logic requirements, where it would integrate multiple standard logic ICs (like 7400-series chips) into a single, compact programmable device. Its common applications included:
System Integration: Replacing multiple discrete logic devices on a board to save space, reduce power consumption, and increase reliability.
Bus Interface Logic: Acting as a bridge between microprocessors and peripheral devices by implementing address decoding, wait-state generation, and bus arbitration.
Communication Systems: Used in networking equipment for signal switching, protocol conversion, and control logic.
Industrial Control: Serving as the core logic for machine control, sensor interfacing, and state machine design in rugged environments.
ICGOODFIND Summary
The Lattice Semiconductor ISPLSI 1016-60LT44 is a classic high-density CPLD that exemplifies the shift from discrete logic to programmable solutions. Its well-designed GLB and GRP architecture, coupled with high-speed performance and crucial in-system programmability, made it an invaluable component for consolidating logic, simplifying board design, and accelerating product development cycles across computing, communications, and industrial sectors.
Keywords: CPLD, In-System Programmability (ISP), Generic Logic Block (GLB), Glue Logic, JTAG
